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High-speed PCB layout guide to practice

Although the printed circuit board (PCB) routing in high-speed circuit has a key role, but it is often the circuit design process, one of the last few steps. There are many aspects of high-speed PCB layout issues have been written on this subject a great deal of literature. In this paper, from a practical point of view to explore the high-speed circuit wiring problems. The main purpose is to help new users to design high-speed circuit PCB layout need to be considered when a variety of issues attention. Another aim is to have no contact with PCB layout for some time to provide a review of information to customers. The paper is limited, this can not be discussed in detail all the issues, but we will discuss improving circuit performance, shorten design time, save the modification time with the greatest impact in a key part.

Although this is mainly aimed at the high-speed op amp circuit, but the issues discussed here and methods used in most other high-speed analog circuit wiring is generally applicable. When the op-amp work in a high radio frequency (RF) band, the circuit performance depends largely on the PCB layout. "Drawing" looks good on the high-performance circuit design, wiring, when due to careless careless if affected, the final can only get the normal performance. Pre-wiring in the whole process of consideration and attention to important details will help to ensure that the desired circuit performance.


Although the fine does not guarantee a good wiring diagram, but a good start on a good wiring diagram. In the schematic drawing when careful consideration, and must consider the whole circuit of the signal flow. If from left to right in the schematic diagram of signal flow with normal and stable, then the PCB, it should also have the same good signal flow. In the schematic diagram is given as much as possible useful information. Because sometimes the circuit design engineer is not, the customer will ask us to help solve the circuit problem, in this work, designers, technicians and engineers would be very grateful, but also we are.

In addition to general reference identifier, power consumption and error tolerance, the principle which the figure should also be given information? Here are some suggestions can be turned into an ordinary first-class schematic diagram. Join the waveform, the shell of mechanical information on the length of printed lines, blank areas; indicating which components need to be placed above the PCB; given adjustment information, component range, heat information, controlled impedance printed lines, notes, briefly The circuit description of action ...... and more.

Do not believe anyone

If not, design your own layout, be sure Go out ample time to carefully check the wiring of people design. At this point of prevention is worth a hundred times a small remedy. Do not expect people to understand your layout ideas. In the early stages of the design process routing of your advice and guidance is most important. The more information you can provide more, and the entire layout process the more you are involved, the result of the PCB, the better. Layout design engineers to set up a tentative completion point - according to a progress report you want to quickly check the wiring. This "closed loop" approach to prevent wiring from going astray, thus the possibility of rework to a minimum.

Wiring instructions of the engineers need to include: a brief description of circuit functions, indicating the location of the input and output PCB sketch, PCB stack information (for example, how thick board, how many layers, the signal layer and ground plane of the detailed information -- power, ground, analog signals, digital signals and RF signals); floors need those signals; require the placement of key components; bypass the exact location of components; which printed line is very important; which need to control the impedance of printed circuit line; which lines need to match the length; component size; which need each other away from the production line (or near); which lines need each other away from (or near); which parts need each other away from (or near); What yuan device to be placed above the PCB, which placed below it. Never complain about other people need to give too much information - too little? Yes; too much? No.

A Learning Experience: About 10 years ago, I designed a multi-layer surface-mount circuit board - the board has components on both sides. Board with a lot of screws will be fixed in a gold-plated aluminum shell (because there are very strict anti-vibration indicators). To provide bias feedthrough pin through the board. This pin is connected to the PCB through the solder on the wire. This is a very complex device. Board on a number of components are used to test the settings (SAT) of the. But I have clearly defined the location of these components. Can you guess what these components are installed in place? Right, and in the board below. When the product engineers and technicians had to disassemble the entire unit to complete the set and then re-assemble them, when looked very unhappy. Since then I have never committed such a mistake.


As in the PCB, the location is everything. Will be a circuit on the PCB on what position would be the specific circuit elements installed in any location, and its adjacent other circuit is what all this is very important.

Typically, input, output and power supply location is pre-determined good, but the circuit between them on the need to "play to their creativity," the. That is why attention to detail will produce a huge return for wiring reasons. The location of key components from the start, according to the specific circuit and the PCB to consider. From the outset, provided the location of key components and signal paths will help ensure that the design to achieve the desired objectives. Once to get the right design can reduce costs and pressure - thus shortening the development cycle.

Bypass Power Supply

In the amplifier's power supply-side bypass in order to reduce PCB design process noise is a very important aspect - including the high-speed op-amp or other high-speed circuits. Bypass high-speed op amp, there are two commonly used configuration.

Power-grounded: In most cases, this method is the most effective use of multiple parallel capacitor op amp power pins directly to ground. Generally speaking, two parallel capacitor is enough - but the increase in shunt capacitor circuit may have some benefits.

Shunt capacitors of different capacitance values help to ensure that the power pin in a very wide frequency band can only see a very low exchange (AC) impedance. This is in the op-amp power supply rejection ratio (PSR) attenuation of frequencies is particularly important. The capacitors help to compensate for amplifier lower PSR. In many 10-octave range to maintain a low-impedance ground path will help to ensure that harmful noise can not enter the op amp. Figure 1 shows the advantages of using multiple parallel capacitors. In the low-frequency, large capacitors provides a low impedance ground path. However, if the frequency of their own resonant frequency, the capacitive capacitor will be weakened, and gradually showing a sensitivity. That is why the use of multiple capacitors are very important reason: When a capacitor frequency response started to decline, the other capacitor frequency response came into play, they are able, in many 10-octave range to maintain a very low AC impedance.

Directly from the op amp power pins to start; with minimal capacitance value and the minimum physical size of capacitors and the op amp should be placed on the same side of PCB - and as close to the amplifier. Capacitor ground terminal should be the shortest possible line of pins or printed directly connected to the ground plane. The ground connection should be as close as possible in order to reduce the load the amplifier power supply side and the interference between the ground terminal. Figure 2 shows such a connection method.

For the second large-value capacitor should repeat the process. The minimum capacitance value is best started from the 0.01mF place, and near the place a 2.2mF (or older) that has a low equivalent series resistance (ESR) of electrolytic capacitors. Using 0508 case size 0.01mF capacitors have very low series inductance and excellent high frequency performance.

Power-ended supply-side: Another method used to configure one or more bypass capacitor connected to the op amp across the positive power supply terminal and a negative power supply terminal between. When the four capacitors in the circuit configuration is very difficult circumstances, often used this approach. Its disadvantage is that the shell of capacitor size may be increased, because the capacitor voltage across a single voltage power supply bypass method twice. Increase the voltage rating of the need to improve the device breakdown voltage, which is to be increased in shell size. However, this method can improve the PSR and distortion performance.

Because each type of circuit and wiring is different, so the capacitor configuration, quantity and capacitance values should be based on the actual circuit request.


The so-called parasitic effects are those that slipped into your PCB and the circuit CUHK Shi damage, headaches, unexplained glitch. They are the hidden penetrate high-speed circuit parasitic capacitance and parasitic inductance. Which includes a long line of package pins and printed to form the parasitic inductance; pad to ground, pad to the power supply plane and the pad to the printed line formed between the parasitic capacitance; through-hole between the effects of as well as many other possible parasitic effects. Figure 3 (a) shows a typical op-amp with the phase diagram. However, if you take into account the parasitic effects, the same circuit may be turned into Figure 3 (b) did.

In high-speed circuit, a small value will affect the circuit performance. Sometimes dozens of leather Act (pF) capacitance is sufficient. Related examples: If the only 1pF inverting input of additional parasitic capacitance, it is almost 2dB frequency domain can lead to sharp pulse (see Figure 4). If the parasitic capacitance is large enough, then it will cause instability and oscillation circuit.

When looking for the parasitic source of the problem, it may Yongde Zhao several above-mentioned parasitic capacitance measurements that the basic formula. Equation (1) is the calculation of the parallel plate capacitor (see Figure 5) formula.

C said capacitance, A expressed in units of cm2 area of the plate, k that the relative dielectric constant of PCB material, d expressed in cm as the unit of distance between plates.

Ribbon inductance is another need to consider the parasitic effects, which is due to production line is too long or the lack of ground plane caused.

Type (2) shows the production line to calculate inductance (Inductance) formula. See Figure 6.

W said the printed line width, L-printed line lengths, H-printed line thickness. All dimensions are in mm as a unit.

Figure 7 shows the oscillation of high-speed op-amp inverting input length of 2.54 cm of the printed line impact. Its equivalent parasitic inductance of 29 nH (10-9H), low enough to cause sustained oscillations will continue until the entire transient response cycle. Figure 7 also shows how to use the ground plane to reduce the parasitic inductance effects.

Through-hole is another parasitic source; they can cause parasitic inductance and parasitic capacitance. Equation (3) is to calculate the parasitic inductance of the formula (see Figure 8).

T said the PCB thickness, d expressed in cm diameter hole for the unit.

Equation (4) shows how to calculate through-hole (see Figure 8) caused by parasitic capacitance value.

er said the PCB materials, the relative permeability. T said the PCB thickness. D1 said that the pad around the hole diameter. D2 said ground plane isolated hole diameter. All dimensions are in cm as a unit. In a 0.157 cm thick, on a through-hole PCB can increase the parasitic inductance of 1.2 nH and 0.5 pF of parasitic capacitance; this is why, when wiring to the PCB must be alert at all times because, to the impact of reduced parasitics to a minimum.

Ground Plane

In fact the contents need to be discussed far more than those mentioned in this article, but we will focus on highlighting some of the key features and to encourage the reader to further explore this issue.

Ground plane to play the role of the public reference voltage to provide shielding, heat dissipation and reduce the parasitic inductance can be (but it will also increase the parasitic capacitance) function. Although the use of the ground plane has many advantages, but must also be careful to achieve, because it can do and can not do have some limitations.

Ideally, PCB layer as a ground plane should be devoted. So that when the plane is not destroyed will produce the best results. Do not diverted in this specific layer in the ground plane area for connecting other signal. As the ground plane can be eliminated between the conductor and ground plane magnetic field, it can reduce the production line inductance. If the destruction of a ground plane area, give ground plane above or below the printing line of the introduction of unexpected parasitic inductance.

Because the ground plane typically have large surface area and cross-sectional area, so the resistance to ground plane to maintain the minimum. In the low-frequency, the current will choose the path of least resistance, but in high frequency, the current will choose the path of least resistance.

However, there are exceptions, and sometimes a small ground plane will be better. If the ground plane from the input or output pad pushed to the next high-speed op-amp will work better. Since the introduction of input parasitic ground plane capacitance, an increase of op-amp's input capacitance, reducing the phase margin, resulting in instability. As in the parasitic effects of a discussion see, the op amp input capacitance of 1 pF can cause obvious spikes. The output capacitive load - including the parasitic capacitive loads - created a feedback loop of the pole. This will reduce the phase margin and cause the circuit to become unstable.

If possible, analog circuits and digital circuits - including their own land and ground plane - should be separated. A fast rising edge will cause current spikes into the ground plane. These fast current spikes caused by noise, would undermine the analog performance. Analog ground and digital ground (and power) should be connected to a common ground point in order to reduce the circulation of digital and analog ground currents and noise.

At high frequency, we must consider a kind of known as the "skin effect" phenomenon. Skin effect will cause current flow to the outer surface of wire - the results will make the wire cross-section of narrow, thus allowing direct current (DC) resistivity. Although the skin effect beyond the scope of this article, here, or copper in the skin depth is given (Skin Depth) a good approximation of the formula (in cm unit):

Low sensitivity of plating metal help reduce skin effect.


Op-amp is usually a different package. The selected package will affect the amplifier's high frequency performance. The main effects include parasitic effects (mentioned earlier) and the signal path. Here we focus on the path to the amplifier input, output and power supply.

Figure 9 shows the use of SOIC package (a) and SOT-23 package (b), the wiring differences between the op amp. Each package has its own problems. Focused look at (a), carefully observe the feedback path found there are many ways to connect feedback. The most important is to ensure that the shortest length of printed lines. Feedback path of the parasitic inductance can cause ringing and overshoot. In Figure 9 (a) and 9 (b), the feedback path around amplifier connection. Figure 9 (c) shows another way - in the SOIC package, the following feedback from the path to connect - thus reducing the feedback path length. Each method has a subtle difference. The first method will lead to production line is too long, could increase the series inductance. The second approach uses through-hole will cause the parasitic capacitance and parasitic inductance. When addressed to PCB layout parasitic effects must be taken into account the impact of its hidden problems. SOT-23 wiring difference is almost ideal: the feedback from the shortest length of printed lines, but little use through-hole; load and bypass capacitor from a very short path to return to the same ground connection; positive supply side of the capacitor (Figure 9 (b) is not shown) directly on the PCB on the back below the negative power supply capacitors.

Low-distortion amplifier pinout: ADI offers some of the operational amplifiers (for example, AD80451) adopted a new low-distortion pinout, help to eliminate the two issues mentioned above; but it also improved the other two important aspect of performance. LFCSP low-distortion pinout, as shown in Figure 10, the traditional op-amp pinout counter-clockwise movement by pressing a pin and adds an output pin as a dedicated feedback pin.

Low-distortion pinout allows the output pins (dedicated feedback pin), and inverting input pins can be close to the connection between, as shown in Figure 11. This greatly simplified and improved layout.

This pin arrangement is that there is an advantage of reducing the second harmonic distortion. Conventional op amp pin configuration second harmonic distortion caused by one of the reasons is the in-phase input and a negative coupling between the supply pins. LFCSP package, low-distortion pinout so to eliminate this coupling greatly reduces second harmonic distortion; in some cases can reduce up to 14 dB. Figure 12 shows the AD80992 with SOIC packages and LFCSP packages distortion performance difference.

This package has one more advantage - low power consumption. LFCSP package has an exposed pad, which reduces the package thermal resistance, which can improve the value of JA is about 40%. Because it reduces the thermal resistance, so reducing the device's operating temperature, also equal to reliability.

Currently, ADI offers a new low-distortion pinout of the three kinds of high-speed op-amp: AD8045, AD8099 and the AD80003.

Wiring and shielding

PCB, there is a wide variety of analog and digital signals, including high to low voltage or current, from DC to GHz frequency range. To ensure that these signals do not interfere with each other is very difficult.

Recalling the earlier "Do not believe anyone else" part of the proposal, the most critical and in order to think in advance how to deal with the signal on the PCB to develop a plan. Important to note what the signal is sensitive to the signal and determine what measures must be taken to ensure signal integrity. Ground plane for the electrical signal to provide a common reference point, but also can be used for shielding. If you need to signal isolation, first printed in the signal should stay out of physical distance between the lines. Here are some practical experience worth learning:

* Reduce the PCB and long parallel lines the same length and signals the proximity between the printed lines can reduce the inductive coupling.

* Reduce the adjacent layer of the length of the long production line can prevent capacitive coupling.

* Require a high degree of signal isolation printed lines should take a different layer, and - if they can not be completely isolated, then - should take the orthogonal printed lines, and will be placed in the ground plane between them. Orthogonal routing can minimize capacitive coupling, and the ground will form an electrical shield. Constitute the controlled impedance printed lines can be used this method.

High-frequency (RF) signals are usually printed in the control line flow impedance. That is, the production line to maintain a characteristic impedance, for example, 50 (RF applications, a typical value). The two most commonly controlled impedance printed lines, microstrip lines 4 and 5 stripline similar effect can be achieved, but achieved in different ways.

Microstrip controlled impedance printed lines, as shown in Figure 13, can be used in any aspect of PCB; it directly using its below ground plane as its reference plane.

Equation (6) can be used to calculate the characteristic impedance of an FR4 board.

H said that the signal produced from the ground plane to the distance between the lines, W said the printed line width, T, said print line thickness; All dimensions are in mils (mils) (10-3 inches) as the unit. er said that the dielectric constant of PCB material.

Ribbon controlled impedance printed line (see Figure 14) using two layers of ground plane, the signal produced in which the clamp. This method uses the more the printing line, the needs of PCB layers more sensitive to the change of dielectric thickness, and higher costs - it is usually used only for demanding applications.

The characteristic impedance for stripline formula such as formula (7) as shown.

Protection ring, or "isolation ring", is another op-amp used shielding method, which is used to prevent parasitic currents access to sensitive nodes. The basic principle is simple - use a wire to protect the sensitive nodes completely surrounded, wire to maintain or to force it to maintain a (low impedance) and the sensitive nodes the same electrical potential, thus allowing absorption of parasitic currents away from sensitive nodes. Figure 15 (a) shows for inverting op amp configuration and the configuration with the phase diagram of the protection ring. Figure 15 (b) shows for the SOT-23-5 package, the two kinds of protection rings typical wiring methods.


High levels of PCB layout for the successful op-amp circuit design is very important, especially for high-speed circuit. A good wiring diagram is a good base; circuit design and layout engineers, design engineers, the close tie between the fundamental, especially with regard to the location of the device and wiring problems. Issues to be considered include the bypass power supply, reducing the parasitic effects, using the ground plane, the impact of op-amp package, as well as wiring and shielding methods.
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